According to GlobalData’s company profile on Winbond Electronics, Magnetic RAMs was a key innovation area identified from patents. Winbond Electronics's grant share as of September 2023 was 77%. Grant share is based on the ratio of number of grants to total number of patents.

High-speed data output and latch circuit resetting in nand flash memory

A recently granted patent (Publication Number: US11775441B2) describes a readout method for a NAND flash memory. The method involves several steps performed in a continuous readout of pages.

The first step is a pre-charging process that pre-charges a bit line and a NAND string connected to the bit line through a sense node. This is followed by a resetting step, where a node of a latch circuit is electrically connected to a reference potential through the sense node, and the latch circuit is reset after the pre-charging.

Next, a discharging step is performed on the NAND string after the resetting. During the continuous readout of pages, data read from a selected page of a memory cell array is held in the latch circuit. After the data is transmitted to another latch circuit, data from the next selected page is held in the latch circuit. The data held in the another latch circuit is continuously outputted to an external part in synchronization with an external clock signal.

The patent also describes an alternative embodiment of the readout method. In this embodiment, the resetting step is performed during the discharging period of the NAND string. The continuous readout of pages and the outputting of data to an external part remain the same as in the previous embodiment.

The patent further details the pre-charging step, which involves generating a voltage for pre-charging at a voltage supply node. The voltage supply node is electrically connected to the sense node through a first select transistor, and the sense node is electrically connected to the bit line through a second select transistor. The resetting step involves generating the reference voltage at the voltage supply node, electrically connecting the voltage supply node to the latch circuit through the first select transistor, and electrically isolating the sense node through the second select transistor.

Additionally, the patent describes a continuous readout process that includes an error check and correction (ECC) process on the data. Data from a first part of the another latch circuit is outputted to the external part while the ECC process is performed on data from a second part. After the data from the first part is outputted, data from the first part of the next selected page is transmitted to the first part of the another latch circuit. Similarly, after the data from the second part is outputted, data from the second part of the next selected page is transmitted to the second part of the another latch circuit.

The patent also discloses a semiconductor apparatus that implements the readout method. The apparatus includes a NAND type memory cell array, a readout component, and an output component. The readout component reads data from a selected page of the memory cell array, while the output component outputs the data to an external part. The readout component includes a page buffer/sense circuit connected to the memory cell array through a bit line. The latch circuit within the page buffer/sense circuit is reset during the discharging period of the NAND string. The page buffer/sense circuit also includes another latch circuit for receiving the data held by the latch circuit, enabling continuous readout of pages.

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