United Microelectronics has filed a patent for a method of fabricating a semiconductor device. The method involves forming inter-metal dielectric layers, creating via holes and a trench, and depositing metal layers to form a metal interconnection and a spin orbit torque layer. The patent claim specifically focuses on forming an opening in the inter-metal dielectric layer and depositing a metal interconnection and spin orbit torque layer within that opening. GlobalData’s report on United Microelectronics gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on United Microelectronics, quantum dot devices was a key innovation area identified from patents. United Microelectronics's grant share as of September 2023 was 81%. Grant share is based on the ratio of number of grants to total number of patents.
Method for fabricating a semiconductor device with metal interconnection
A recently filed patent (Publication Number: US20230320232A1) describes a method for fabricating a semiconductor device. The method involves several steps, including forming a first inter-metal dielectric (IMD) layer on a substrate, creating an opening in the first IMD layer, and then forming a metal interconnection and a spin orbit torque (SOT) layer within the opening.
The method also includes additional steps, such as forming two via holes and a trench in the first IMD layer, depositing a metal layer in the via holes and trench to create the metal interconnection and SOT layer, and forming a magnetic tunneling junction (MTJ) on the SOT layer. Furthermore, the method involves the formation of hard masks, a cap layer, and a second IMD layer around the MTJ.
In an alternative embodiment, the method includes forming a second IMD layer on the substrate, creating two via holes in the second IMD layer, forming the metal interconnection in the via holes, and then forming a third IMD layer on top. A trench is created in the third IMD layer, and the SOT layer is formed within the trench. Similar to the previous embodiment, an MTJ, hard masks, a cap layer, and a fourth IMD layer are also included.
The resulting semiconductor device comprises a first IMD layer on the substrate, with the metal interconnection and SOT layer within the first IMD layer. The top surfaces of the first IMD layer and the SOT layer are coplanar. Additionally, the device includes an MTJ, hard masks, a cap layer, and a second IMD layer around the cap layer.
In the alternative embodiment, the semiconductor device includes a second IMD layer on the substrate, with the metal interconnection in the second IMD layer. The SOT layer is within a third IMD layer, and the top surfaces of the third IMD layer and the SOT layer are coplanar. The device also includes an MTJ, hard masks, a cap layer, and a fourth IMD layer.
It is worth noting that the metal interconnection and SOT layer can be made of the same material, such as tungsten, in both embodiments.
Overall, this patent describes a method for fabricating a semiconductor device with specific layers and structures, as well as the resulting semiconductor device itself. The disclosed method and device may have potential applications in the field of semiconductor manufacturing.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
