Taiwan Semiconductor Manufacturing had one patents in edge computing during Q4 2023. The patent filed by Taiwan Semiconductor Manufacturing Co Ltd in Q4 2023 relates to methods and computer-readable media for resistance and capacitance (RC) extraction from electronic layouts. The method involves selecting a 2D conductive element, partitioning it into polygons, determining parasitic capacitance and resistance values for each polygon, and calculating the total capacitance and resistance values of the 2D conductive element. GlobalData’s report on Taiwan Semiconductor Manufacturing gives a 360-degreee view of the company including its patenting strategy. Buy the report here.
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Taiwan Semiconductor Manufacturing grant share with edge computing as a theme is 0% in Q4 2023. Grant share is based on the ratio of number of grants to total number of patents.
Recent Patents
Application: Parasitic resistance and capacitance extraction methods and non-transitory computer-readable media thereof (Patent ID: US20230367945A1)
The patent filed by Taiwan Semiconductor Manufacturing Co Ltd. discloses methods and a computer-readable medium for resistance and capacitance (RC) extraction. The method involves receiving an electronic layout, selecting a two-dimensional conductive element with a low aspect ratio, partitioning it into polygons, determining parasitic capacitance and resistance values for each polygon, and calculating the total capacitance and resistance values of the 2D conductive element based on these parameters. The method is applicable to various types of 2D conductive elements, including metal plates and metal insulator metal (MIM) capacitors, and involves partitioning polygons into triangles or rectangles, with edge lengths optimized for specific operating frequencies.
Furthermore, the patent extends the method to three-dimensional conductive elements, involving the partitioning of polyhedrons into tetrahedrons and cuboids to determine parasitic capacitance and resistance values. The non-transitory computer-readable medium stores program instructions for executing these operations, including determining parasitic capacitance based on polygon area, partitioning polygons into triangles, and further partitioning triangles into rectangles to calculate resistance values. This innovative approach to RC extraction offers a comprehensive and efficient method for analyzing the electrical characteristics of both 2D and 3D conductive elements in electronic layouts, providing valuable insights for semiconductor manufacturing processes.
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