Taiwan Semiconductor Manufacturing had 280 patents in advanced materials during Q4 2023. The patents filed by Taiwan Semiconductor Manufacturing Co Ltd in Q4 2023 cover methods for manufacturing semiconductor devices with nanowires, improving sealing between contact plugs and dielectric layers, gate structures wrapped around nanostructures, forming a complementary metal oxide semiconductor (CMOS) device by bonding transistors of different types, and an IC structure with transistors, gate spacers, backside metal lines, and metal contacts. GlobalData’s report on Taiwan Semiconductor Manufacturing gives a 360-degreee view of the company including its patenting strategy. Buy the report here.
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Taiwan Semiconductor Manufacturing grant share with advanced materials as a theme is 37% in Q4 2023. Grant share is based on the ratio of number of grants to total number of patents.
Recent Patents
Application: Method of manufacturing a semiconductor device and a semiconductor device (Patent ID: US20230411215A1)
The patent filed by Taiwan Semiconductor Manufacturing Co Ltd describes a method for manufacturing a semiconductor device involving the formation of multiple semiconductor layers with varying compositions over a substrate. These layers are then patterned to create a fin structure, from which a nanowire is formed by removing a portion of one of the layers. The resulting nanowire is surrounded by a conductive material. The semiconductor layers consist of different materials, with specific concentrations of Si and Ge in each layer.
The semiconductor device described in the patent consists of a stack of semiconductor layers arranged perpendicular to the substrate, with a gate electrode layer wrapping around them. Each semiconductor layer comprises inner and outer layers made of Si and Ge, with different concentrations of these elements. The inner layer is thicker than the outer layers, and the overall structure includes insulating sidewalls, a bottom fin structure, and a high-k dielectric layer. Another embodiment of the device involves a gate structure wrapping around the semiconductor layers, with the layers consisting of different Group IV elements and specific thickness ranges for each layer. The device also includes insulating sidewalls and a high-k dielectric layer for improved performance.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
