Sino-American Silicon Products has been granted a patent for their method of producing single crystal silicon ingots using Continuous Czochralski (CCz) process. The method involves adding a batch of quartz cullets to the melt before the main body of the ingot is grown, and controlling the ratio of the mass of the batch to the time between adding the batch and the start of growth. This helps reduce void counts in wafers sliced from the ingot. The patent also includes adding solid polycrystalline silicon feedstock to replenish the melt during the process. GlobalData’s report on Sino-American Silicon Products gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Sino-American Silicon Products, Artificial photosynthesis was a key innovation area identified from patents. Sino-American Silicon Products's grant share as of September 2023 was 46%. Grant share is based on the ratio of number of grants to total number of patents.
Method for growing single crystal silicon ingots with reduced void counts
A recently granted patent (Publication Number: US11767610B2) describes a method for growing a single crystal silicon ingot in a continuous Czochralski process. The method involves several steps to reduce void counts in wafers sliced from the single crystal silicon ingot.
The method begins by forming a melt of silicon in a crucible assembly and adding a batch of quartz cullets to the melt. The ratio of the mass of the batch of quartz cullets to the time between adding the batch and the start of growth of the main body of the ingot (M/T) is controlled to be greater than a threshold value. This helps to reduce void counts in the resulting wafers.
The patent claims that by controlling the M/T ratio to be greater than the threshold value, the wafers sliced from the single crystal silicon ingot will have a void count of less than either 30 voids or 20 voids of a size of 0.2 µm or more, depending on the specific claim.
The threshold M/T value can be determined by growing multiple single crystal silicon ingots with different M/T ratios and measuring the void count in the resulting wafers. The threshold void count is set at either 30 voids or 20 voids of a size of 0.2 µm or more, depending on the specific claim.
The patent also describes the addition of solid polycrystalline silicon feedstock to the crucible assembly while withdrawing the single crystal silicon ingot to replenish the melt. This ensures a continuous growth process.
The method can be applied to subsequent single crystal silicon ingots as well, by adding a second batch of quartz cullets and controlling the M/T ratio to reduce void counts in wafers sliced from the second ingot.
The crucible assembly used in the method includes a weir and a sidewall that define an outer melt zone, where the batch of quartz cullets is added. There can also be additional weirs that define middle and inner melt zones.
Overall, this patent presents a method for growing single crystal silicon ingots with reduced void counts in the resulting wafers. By controlling the M/T ratio and adding quartz cullets to the melt, the method aims to improve the quality of silicon wafers used in various electronic applications.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
