Silicon Laboratories has filed a patent for a phase-locked loop (PLL) that provides a local oscillator signal for a radio. The PLL includes control logic that responds to a request to change the oscillator output signal by setting capacitor circuits of the oscillator to specific values based on temperature and frequency difference. The PLL then locks to the new frequency using a signal from the PLL loop filter to adjust another capacitor circuit. GlobalData’s report on Silicon Laboratories gives a 360-degree view of the company including its patenting strategy. Buy the report here.
According to GlobalData’s company profile on Silicon Laboratories, Low Energy IoT network protocols was a key innovation area identified from patents. Silicon Laboratories's grant share as of September 2023 was 76%. Grant share is based on the ratio of number of grants to total number of patents.
A pll method for generating an oscillator output signal
A recently filed patent (Publication Number: US20230318609A1) describes a method and apparatus for generating an oscillator output signal with a desired frequency using a phase-locked loop (PLL). The method involves receiving a request for the oscillator to generate the output signal at a specific frequency. The first frequency control parameter of the oscillator is set to a predetermined value corresponding to the requested frequency. Additionally, the second frequency control parameter of the oscillator is set based on the frequency difference between the predetermined frequency and the requested frequency, as well as the measured temperature.
The patent also describes the use of capacitance values to control the frequency of the oscillator. The first frequency control parameter is associated with a first capacitance in a first capacitor circuit, while the second frequency control parameter is associated with a second capacitance in a second capacitor circuit. These capacitance values are adjusted to ensure that the oscillator frequency falls within the tuning range of the PLL, which is controlled by a third frequency control parameter.
The apparatus described in the patent includes a phase-locked loop with an oscillator, control logic, and various capacitor circuits. The control logic receives a request to generate an oscillator output signal at a desired frequency and sets the capacitance values in the capacitor circuits accordingly. The control logic also utilizes lookup tables to determine the appropriate capacitance values based on the frequency difference and temperature measurements.
Furthermore, the patent discusses the use of variable capacitor arrays in the second capacitor circuit. The control logic sets the capacitance values of these arrays based on the frequency difference and temperature measurements. The apparatus also includes a local oscillator circuit and a mixer circuit, which are used in a radio receiver circuit.
The patent also describes a method for determining a frequency estimate of the oscillator output signal before the PLL locks to the desired frequency. This estimate is used to maintain or modify a control code associated with the second capacitance. If the frequency estimate falls within a certain range, the control code remains unchanged. However, if the estimate is outside this range, the control code is modified to adjust the capacitance values.
Additionally, the patent discusses the ability to change the bandwidth of the PLL while it is locked to the desired frequency. This allows for more precise control over the oscillator output signal.
Overall, the patent presents a method and apparatus for generating an oscillator output signal with a desired frequency using a phase-locked loop. The use of capacitance values and variable capacitor arrays allows for precise control over the oscillator frequency, while the ability to adjust the PLL bandwidth enhances the accuracy of the output signal.
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