Rambus. has been granted a patent for a buffer circuit that includes a command address interface and adaptive repair circuitry. This circuitry stores failure address information and updates it upon detecting new errors, optimizing memory operations by managing known failure addresses during data transfers. GlobalData’s report on Rambus gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Rambus, M2M communication interfaces was a key innovation area identified from patents. Rambus's grant share as of June 2024 was 68%. Grant share is based on the ratio of number of grants to total number of patents.
Adaptive repair circuitry for memory devices in integrated circuits
The patent US12040035B2 describes an integrated circuit (IC) chip designed to enhance memory device reliability through adaptive repair mechanisms. The chip features a primary interface for communication with a memory controller and a secondary interface for connecting to memory devices. Central to its functionality is adaptive repair circuitry that stores known failure address information during normal operations. This circuitry includes update mechanisms that respond to newly detected error addresses, allowing the chip to selectively incorporate these new addresses into its known failure information, contingent upon the availability of repair resources. The repair resources may consist of substitute storage locations, which can include on-chip static random access memory (SRAM) configured to store data for known failure locations.
Additionally, the patent outlines a buffer circuit with similar functionalities, emphasizing the importance of error detection and the adaptive updating of failure address information. The buffer circuit also utilizes on-chip SRAM for substitute storage and incorporates state bits to manage access to these storage locations based on prior write operations. The method of operation for the buffer circuit includes transferring information with a memory controller, interfacing with memory devices, and adaptively repairing memory by detecting new error addresses and updating known failure information accordingly. The design aims to improve data integrity and operational efficiency in memory systems by addressing potential failures dynamically.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
