Rambus has filed a patent for a memory controller that issues refresh management commands to a memory device to prevent data corruption caused by “row hammer.” The commands are associated with specific row addresses and are issued based on the number of activate commands issued since the last refresh management command. The patent claims an unequal number of row activate commands between refresh management commands. GlobalData’s report on Rambus gives a 360-degree view of the company including its patenting strategy. Buy the report here.
According to GlobalData’s company profile on Rambus, M2M communication interfaces was a key innovation area identified from patents. Rambus's grant share as of September 2023 was 69%. Grant share is based on the ratio of number of grants to total number of patents.
Refresh management commands to mitigate data corruption caused by row hammer
A recently filed patent (Publication Number: US20230317136A1) describes a memory controller that includes a command interface and control circuitry. The command interface is responsible for transmitting row activate (ACT) commands and refresh management (RFM) commands to a memory device. The control circuitry determines the number of row activate commands to be transmitted between consecutive refresh management commands, ensuring that the first and second numbers are not equal.
The memory controller also receives an indicator from the memory device associated with a third number of row activate commands. In this case, the first number is greater than the third number, and the second number is less than the third number. Additionally, the average of the first and second numbers is not equal to the third number.
The memory device selects row addresses based on the received row activate commands. For example, it selects a first row address from a set of row addresses received between the first and second refresh management commands. Based on this first row address, the memory device selects at least a second row address to be refreshed. Similarly, it selects a third row address from a different set of row addresses received between the second and third refresh management commands, and based on this third row address, selects at least a fourth row address to be refreshed.
The memory controller also includes a randomized selection technique for choosing row addresses. This technique is used to select the first row address from the set of row addresses received between the first pair of consecutive refresh management commands. It is also used to select the third row address from the set of row addresses received between the second pair of consecutive refresh management commands.
In summary, the patent describes a memory controller that efficiently manages the transmission of row activate commands and refresh management commands to a memory device. The controller ensures that the number of row activate commands between consecutive refresh management commands is unequal and uses a randomized selection technique for choosing row addresses. This technology aims to improve the performance and efficiency of memory devices.
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