Taiwan Semiconductor Manufacturing Company (TSMC), the world’s largest chipmaker, has reportedly kicked off pilot production of its 3-nanometre (3nm) process at its Fab 18 plant in southern Taiwan. It expects to produce the high-end chip in volume by the fourth quarter of 2022, according to DigiTimes Asia, citing industry sources.
It was reported last month that Apple will be the first client to use the 3nm chips in forthcoming products. Currently, the California-based company uses TSMC’s 5nm process to produce its M1 chips. Other notable clients in line for TSMC’s newest chip include Intel, AMD and Qualcomm.
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In June, TSMC started trial production of its 4nm chip. At the same time, it also said it would begin mass production of its 3nm semiconductor in the second half of 2022.
According to the company, the 3nm chip offers up to 70% logic density gain, up to 15% speed improvement at the same power and up to 30% power reduction at the same speed as its 5nm technology. It added that the new process would feature reliable fin field-effect (FinFET) transistor architecture to support the best performance, power efficiency and cost-effectiveness.
Despite being the largest chipmaker globally, TSMC has admitted that it still faces major hurdles when it comes to advanced packaging. At an event hosted by the International Semiconductor Industry Association (SEMI), Douglas Yu, TSMC’s Vice President of R&D, said that heterogeneous integration in semiconductors will be the future development trend.
On November 30, TSMC revealed its 3D Fabric platform, which it says will lead the industry in heterogeneous integration and system miniaturisation. Although TSMC is rapidly advancing its capacity to shrink nodes beyond 3nm, when it comes to advanced packaging, the company is admittedly lacking behind.
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By GlobalDataFor decades, chip manufacturers have added more transistors – the key component of semiconductors – onto ever smaller areas. Following Moore’s law, the number of transistors in a given area doubles roughly every two years. However, this phenomenon has slowed down in recent times, with the number of transistors packed on a tiny surface pushing the laws of physics.
It is important to note that both the terms 3nm and 5nm have no relation to the physical size of the component gates on the chip. Instead, such labels have become a marketing strategy used to suggest a chip’s increased speed and power efficiency.
The next big chip development concerns advanced packaging. With transistor density now constrained on a single 2D flat surface, most chip manufacturers are exploring 3D options, where multiple layers are stacked atop one another. This permits more transistors to be added without needing to make them even smaller or to increase the area of a layer, which would lead to delays in communication between different parts of the chip.
3D methods are now near-universal in flash memory chips, but it is proving more difficult to implement them in processors and RAM. The key to success is considered to be integration of heterogenous materials, allowing chips to be packaged and stacked in layers while still permitting the layers to communicate with one another sufficiently speedily. This is the problem that TSMC has struggled to solve. Nevertheless, Yu’s announcement indicates that the company is actively advancing in this area.
According to GlobalData’s semiconductor sector scorecard, TSMC is the world’s largest chip foundry, making bespoke logic chips for companies that provide their own designs. The company, founded in 1987 and headquartered in Hsinchu, Taiwan, is one of the top ten thematic leaders in the industry.
TSMC is also a global powerhouse. It recently announced, in partnership with Japanese tech conglomerate Sony, that it would build a $7bn chip plant in Japan. Earlier this year, the company broke ground at its $12bn factory in Phoenix, Arizona.
The EU is now also trying to persuade the Taiwanese chip giant to set up shop in the region. TSMC recently said it was considering Germany as the destination for its first European factory. Last week, Kung Ming-hsin, Taiwan’s National Development Council boss, told reporters that plans are underway to see if Taiwan could collaborate with three Eastern European nations – Slovakia, the Czech Republic and Lithuania – on semiconductors.
