Murata Manufacturing has been granted a patent for methods and apparatuses to control the gain of a single stage cascode FET amplifier. The patent describes using a series-connected resistor and capacitor to control the gain, with the resistor being a variable resistor that can be adjusted to provide different gains. The patent also mentions using an input matching network to compensate for different noise figure degradations. The amplifier circuit described in the patent includes an input transistor, an output transistor, and a series connected capacitor and resistor. The circuit’s gain is provided by a resonance between the inductive source impedance and the capacitive drain impedance. GlobalData’s report on Murata Manufacturing gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Murata Manufacturing, Battery management systems was a key innovation area identified from patents. Murata Manufacturing's grant share as of September 2023 was 42%. Grant share is based on the ratio of number of grants to total number of patents.
Amplifier circuit with gain control using resistor and capacitor
A recently granted patent (Publication Number: US11777451B2) describes an amplifier circuit that operates as a single-stage amplifier. The circuit includes an input transistor and an output transistor, with a series connected capacitor and resistor between the gate of the output transistor and a reference ground. The series connected capacitor and resistor create an inductive source impedance for the output transistor, while the drain impedance at the input transistor is capacitive. The gain of the amplifier circuit is achieved through resonance between the inductive source impedance and the capacitive drain impedance.
The amplifier circuit is designed to operate within a frequency range of 4 GHz to 5 GHz, or from DC to 15 GHz, depending on the specific implementation. The value of the resistor in the circuit can range from 5 Ohms to 20 Ohms or 30 Ohms, and it is configured to provide a higher gain compared to a resistor value of zero Ohms. The gain of the amplifier circuit can be increased by approximately 2 dB with the appropriate resistor value.
The amplifier circuit can also function as a low noise amplifier, with additional components such as a degeneration inductor coupled between the source of the input transistor and the reference ground. An input inductor and an input matching network can be coupled to the gate of the input transistor to further optimize performance.
The resistor in the circuit can be a variable resistor, allowing for flexibility in adjusting the gain and performance of the amplifier circuit. A configurable input matching network can be coupled to the gate of the input transistor to enhance the versatility of the circuit.
The patent also mentions the use of field-effect transistors (FETs) as the input and output transistors in the amplifier circuit.
The amplifier circuit described in the patent can be incorporated into a communication system that operates across multiple frequency bands, spanning from 4 GHz to 5 GHz.
The patent also covers a monolithically integrated circuit that includes the amplifier circuit, as well as an electronic module that incorporates this integrated circuit.
The patent further describes a method for operating the amplifier circuit, which involves coupling a capacitor and resistor in series between the gate of a first transistor and a reference ground to create an inductive impedance at the source of the first transistor. The drain of a second transistor is then connected to the source of the first transistor, generating resonance between the capacitive impedance at the drain of the second transistor and the inductive impedance at the source of the first transistor. This method allows for the amplification of an RF signal at the drain of the first transistor.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
