MegaChips has been granted a patent for a non-volatile storage system that performs high-speed error correction processing. The system reads data from a non-volatile storage device and performs error correction decoding. If the decoding fails, the system performs diversity synthesis processing on the data and repeats the error correction processing. This ensures both speed and error correction capability in the storage system. GlobalData’s report on MegaChips gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on MegaChips, Cloud gaming was a key innovation area identified from patents. MegaChips's grant share as of September 2023 was 49%. Grant share is based on the ratio of number of grants to total number of patents.
Non-volatile storage system with high-speed error correction processing
A recently granted patent (Publication Number: US11776652B2) describes a non-volatile storage device with improved error correction capabilities. The device includes a memory interface circuitry that performs data write and readout processing, as well as an error correction processing circuitry that performs error correction code decoding processing on data read from the non-volatile memory.
When the error correction code decoding processing is successful, the error correction processing circuitry outputs the data obtained through the decoding process. However, if the decoding process fails, the memory interface circuitry reads the data from the non-volatile memory again. In this case, the error correction processing circuitry performs diversity synthesis processing, which involves synthesizing the data read for the first time and the data read for the second time from the same address. The error correction code decoding processing is then performed on the data obtained through the diversity synthesis process. If the decoding is successful, the data obtained through the decoding process is outputted. If the decoding fails again, the memory interface circuitry reads the data from the non-volatile memory once more and repeats the diversity synthesis and error correction code decoding processes.
The patent also describes additional features of the non-volatile storage device. When the decoding of the error correction code fails during the diversity synthesis process, the memory interface circuitry adjusts the threshold voltage when reading data from the non-volatile memory and reads the data again. The adjustment of the threshold voltage can be lower or higher than a reference threshold voltage, depending on whether the memory cell has been greatly affected by data retention or read disturbance.
Furthermore, the patent includes a data readout method for the non-volatile storage device. The method involves the steps of successful error correction code decoding, repeated data reading and synthesis, and repeated error correction code decoding. The method can be executed by a computer through a non-transitory computer readable storage medium.
Overall, this patent presents a non-volatile storage device with enhanced error correction capabilities, allowing for improved data reliability and integrity. The device employs diversity synthesis processing and threshold voltage adjustments to address decoding failures and memory cell issues.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
