According to GlobalData’s company profile on MediaTek, Adaptive video coding was a key innovation area identified from patents. MediaTek's grant share as of September 2023 was 60%. Grant share is based on the ratio of number of grants to total number of patents.

Memory system training method with clock signal and data signals

A recently granted patent (Publication Number: US11776613B2) describes a memory controller that generates multiple signals to a memory. The memory controller outputs a clock signal and command/address signals to the memory and receives either a first sampled content or a second sampled content through a plurality of data signals from the memory in response to a control signal. The memory controller is specifically designed to program a specified bit of a mode register of the memory using the control signal. This specified bit is referred to as a phase select bit, and the mode register also includes a command bus training mode bit.

The memory controller includes n pins to transmit the command/address signals and m pins to transmit the plurality of data signals. It is important to note that m is larger than n, and m is smaller than 2n. The memory itself is configured to output the first sampled content when the control signal is in a first state, and it outputs the second sampled content when the control signal is in a second state. The memory controller is responsible for transmitting the control signal to the memory.

In some embodiments, one of the data signals in the plurality of data signals can also serve as the control signal. The first sampled content is sampled in response to a first type of clock signal edge, while the second sampled content is sampled in response to a second type of clock signal edge. Specifically, the first type is a rising edge, and the second type is a falling edge. These rising and falling edges of the clock signal are consecutive edges.

The memory controller described in the patent is primarily designed to control a DRAM (Dynamic Random Access Memory). It can receive the first sampled content and the second sampled content through different data signals simultaneously or sequentially. In both cases, the first sampled content is sampled in response to a first type of clock signal edge, and the second sampled content is sampled in response to a second type of clock signal edge. Again, the first type is a rising edge, and the second type is a falling edge. These rising and falling edges of the clock signal are consecutive edges.

Overall, this patent presents a memory controller that efficiently generates signals to a memory and allows for the programming of specific bits in the memory's mode register. The controller is designed to work with a DRAM and can handle different types of clock signal edges for sampling data content.

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