NXP Semiconductors had 48 patents in future of work during Q1 2024. The patents filed by NXP Semiconductors NV in Q1 2024 include a multiphase digital frequency synthesizer, a phase-shift to duty-cycle converter system, a sigma-delta ADC design, a method for controlling a frequency-modulated oscillator in a phase-locked loop circuit, and a digitally controlled DC-DC converter with a power stage and controller for generating an output voltage. These inventions involve various circuitry and methods for efficient frequency synthesis, analog-to-digital conversion, and power conversion. GlobalData’s report on NXP Semiconductors gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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NXP Semiconductors grant share with future of work as a theme is 56% in Q1 2024. Grant share is based on the ratio of number of grants to total number of patents.
Recent Patents
Application: Multiphase digital frequency synthesizer with fractional division (Patent ID: US20240088879A1)
The patent filed by NXP Semiconductors NV describes a multiphase digital frequency synthesizer that includes a multiphase ring oscillator, clock divider, positive select circuitry, carry circuitry, positive multiplex circuitry, and fractional phase addition circuitry. The system operates by dividing a phased clock signal, accumulating a positive select value with a fractional division factor, determining the carry value, selecting phased clock signals, and providing an output clock signal based on these operations. The system also includes negative select circuitry and duty cycle correction circuitry for additional functionalities.
The multiphase digital frequency synthesizer utilizes a multiphase ring oscillator to provide phased clock signals, a clock divider to divide the signals, positive select circuitry to accumulate values, carry circuitry to determine carry values, positive multiplex circuitry to select clock signals, and fractional phase addition circuitry to generate output clock signals. The system also incorporates negative select circuitry and duty cycle correction circuitry for further enhancements. The method involves dividing clock signals, accumulating values, selecting clock signals, and providing output signals based on the accumulated values and selected clock signals, with additional steps for duty cycle adjustment and negative signal selection.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
