NXP Semiconductors has patented a self-test mechanism for integrated circuits to evaluate clock signal monitoring units. The method involves injecting faults to test if the unit operates within specified parameters. This innovation ensures accurate clock signal monitoring. GlobalData’s report on NXP Semiconductors gives a 360-degree view of the company including its patenting strategy. Buy the report here.
According to GlobalData’s company profile on NXP Semiconductors, Quantum dot devices was a key innovation area identified from patents. NXP Semiconductors's grant share as of April 2024 was 65%. Grant share is based on the ratio of number of grants to total number of patents.
Self-test mechanism for clock monitor unit in integrated circuit
A recently granted patent (Publication Number: US11971447B2) discloses a method for operating a clock monitor unit within an integrated circuit. The method involves performing comparisons of the clock signal's operating frequency to specified frequency ranges during different measurement windows. By selectively asserting or deasserting event signals based on these comparisons, the clock monitor unit can detect faults and indicate successful or failed fault detection. The patent also details a fault injection operating mode where thresholds defining the frequency range are modified to simulate faults, allowing for comprehensive testing of the clock monitor unit's functionality.
Furthermore, the integrated circuit described in the patent includes logic circuitry, a clock source providing the clock signal, and the clock monitor unit responsible for monitoring the clock signal. The clock monitor unit conducts multiple comparisons of the operating frequency to high and low frequency threshold values in both functional and fault injection operating modes. By generating event signals and a clock fail signal, the clock monitor unit can indicate whether it is functioning within specified operating parameters. In cases where the unit is not operating correctly, additional measures such as deactivating the clock monitor unit can be implemented based on the generated signals. This innovative method and system provide a robust approach to ensuring the proper functioning of clock monitoring units within integrated circuits.
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