Global Foundries. has been granted a patent for a semiconductor structure featuring a silicon substrate with alternating Pwell and Nwell regions, a deep Nwell, and an Nwell-type isolation region. This design allows for electrically isolated sections, enabling different back-biasing conditions for devices formed on an insulator layer above. GlobalData’s report on Global Foundries gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Global Foundries, Quantum dot devices was a key innovation area identified from patents. Global Foundries's grant share as of June 2024 was 79%. Grant share is based on the ratio of number of grants to total number of patents.
Semiconductor structure with isolated well regions for devices
The granted patent US12046603B2 describes a semiconductor structure that incorporates a silicon substrate with a deep Nwell and alternating Pwells and Nwells arranged in elongated parallel stripes. This configuration allows for the Pwell regions to be positioned laterally between Nwells, facilitating the creation of silicon-on-insulator (SOI) regions and bulk regions that traverse these alternating wells in a perpendicular direction. A notable feature of this structure is the inclusion of an Nwell-type isolation region, which divides a Pwell into distinct sections, enabling different voltage levels to be applied to these sections. This design enhances the electrical performance of the semiconductor by allowing for biasing at varying voltage levels, which is particularly beneficial for optimizing the operation of devices situated above these regions.
Additionally, the patent outlines various configurations and enhancements to the semiconductor structure, including the potential for multiple Nwell-type isolation regions and trench isolation regions that extend vertically and laterally within the substrate. The structure supports both P-type and N-type field effect transistors (FETs) in the SOI regions, with the ability to connect different sections of the Pwell to separate voltage sources. This arrangement allows for the integration of diverse groups of FETs, including stacked configurations for specific applications. The claims emphasize the versatility of the semiconductor structure, which can be tailored for improved performance in electronic devices by leveraging the unique arrangement of wells and isolation regions.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
