AUO has been granted a patent for a chip mass transfer device featuring a first substrate with a chip-connecting area and a patterned recess, along with a second substrate designed for chip attachment. The innovation aims to enhance the efficiency of chip transfer processes. GlobalData’s report on AUO gives a 360-degree view of the company including its patenting strategy. Buy the report here.
According to GlobalData’s company profile on AUO, Under-screen fingerprint recognition was a key innovation area identified from patents. AUO's grant share as of June 2024 was 79%. Grant share is based on the ratio of number of grants to total number of patents.
Mass transfer device for connecting semiconductor chips
The patent US12046496B2 describes a device designed for the mass transfer of semiconductor chips. The device consists of two substrates: a first substrate featuring a chip-connecting area on its first surface and a patterned recess on its second surface. This recess includes a patterned through hole that connects both surfaces, with its projection on the first surface positioned away from the chip-connecting area. The second substrate has a chip-receiving area on its third surface, which is intended for attaching the chip from the first substrate. The claims emphasize the spatial arrangement of the patterned through hole relative to the chip-connecting area, ensuring effective chip transfer.
Further claims detail the construction of the second substrate, which includes two adhesive layers. The first adhesive layer supports the third surface, while the second adhesive layer is located on the fourth surface. A laser source is incorporated into the device, designed to interact differently with the two adhesive layers, allowing for selective absorption. Specifically, the laser is absorbed by the first adhesive layer while passing through the second adhesive layer, with a specified wavelength of approximately 355 nanometers. Additionally, the thickness of the second adhesive layer is designed to be 20% to 50% greater than that of the first adhesive layer, optimizing the device's functionality in chip transfer applications.
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