Marvell Technology. has been granted a patent for clock data recovery circuitry in a data transceiver deserializer. The invention features a clock recovery loop with a first feed-forward equalizer and a data recovery loop with a second equalizer, enhancing clock signal recovery through their interconnected outputs. GlobalData’s report on Marvell Technology gives a 360-degree view of the company including its patenting strategy. Buy the report here.

According to GlobalData’s company profile on Marvell Technology, Network virtualization was a key innovation area identified from patents. Marvell Technology's grant share as of July 2024 was 79%. Grant share is based on the ratio of number of grants to total number of patents.

Clock data recovery circuitry for data transceivers

Source: United States Patent and Trademark Office (USPTO). Credit: Marvell Technology Inc

The granted patent US12074961B1 outlines a novel clock data recovery circuitry designed for a deserializer in a data transceiver. The circuitry features a clock recovery loop and a data recovery loop, each utilizing feed-forward equalizers with differing numbers of taps. The clock recovery loop employs a first feed-forward equalizer to extract a clock signal from received data, while the data recovery loop utilizes a second feed-forward equalizer with a greater number of taps to recover the data signal. The outputs of both equalizers are interconnected to enhance the clock signal recovery process. Additionally, the data recovery loop incorporates a decision feedback equalizer to adapt the coefficients of the second feed-forward equalizer, while the clock recovery loop includes adaptation circuitry to mitigate any adverse effects on the clock signal caused by the data recovery process.

Further claims detail the integration of various components, such as data slicers and error detection mechanisms, to refine the clock and data recovery processes. The clock recovery loop includes a timing error detector and slicer error circuitry to adjust the coefficients of the first feed-forward equalizer based on detected errors. The data recovery loop similarly features a second data slicer and corresponding error circuitry to optimize the recovery of the data signal. The patent also describes gain control circuitry for both feed-forward equalizers, which can be either integral or separate, and emphasizes the adaptability of these components to improve performance. Additionally, a third feed-forward equalizer is proposed to address reflections in the impulse response of the circuitry, further enhancing the overall efficacy of the clock data recovery system.

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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.