SiFive has been granted a patent for checker cores in fault-tolerant processing. The integrated circuit includes a processor core, outer memory system, and checker core to detect errors in instruction packets. An architectural state injection circuit triggers a pipeline flush and transfers corrected data in case of errors. GlobalData’s report on SiFive gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on SiFive, Vector processing optimization was a key innovation area identified from patents. SiFive's grant share as of May 2024 was 4%. Grant share is based on the ratio of number of grants to total number of patents.
Fault tolerant processing using checker cores in integrated circuits
A recently granted patent (Publication Number: US11966290B2) discloses an integrated circuit designed to enhance error detection and correction in instruction execution. The circuit includes a processor core, an outer memory system, a checker core, and an architectural state injection circuit. The checker core checks committed instruction packets for errors and, upon detection, triggers a pipeline flush in the processor core and transfers a corrected portion of the architectural state from the checker core to the processor core. Additionally, an error detection circuit within the memory pathway of the processor core is configured to detect errors in data passing through, implementing techniques such as parity checks and error-correcting codes.
Furthermore, the patent details a method involving the checker core decoding and executing instructions from committed packets, comparing results, and responding to errors by injecting the checker core's architectural state into the processor core. The method also includes features like sending error messages to interrupt handlers and comparing program counters. The non-transitory computer-readable medium described in the patent provides a circuit representation for programming or manufacturing the integrated circuit, emphasizing the limited data flow between the processor core and checker core, the formal verification of the checker core, and the specific timing of instruction commitments between the cores. Overall, the patent aims to improve error detection and correction mechanisms in integrated circuits, particularly in the context of instruction execution.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
