Micron Technology has filed a patent for an apparatus, system, and method for a row decoder with multiple section enable signal voltage domains. The invention involves decoding a row address into a pre-enable signal and generating first and second section enable signals based on the pre-enable signal. These signals are in different voltage domains, with the second voltage being between the first and third voltages. A word line driver signal is then generated based on the section enable signals. The patent claim describes an apparatus with a section enable signal driver and a section enable circuit that provide section enable signals in different voltage domains and generate a multi-word line driver signal based on these signals. GlobalData’s report on Micron Technology gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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Row decoder with multiple section enable signal voltage domains
A recently filed patent (Publication Number: US20230317141A1) describes an apparatus and method for generating multi-word line driver signals in different voltage domains. The apparatus includes a section enable signal driver that receives a pre-section enable signal and provides a first section enable signal in a first voltage domain and a second section enable signal in a second voltage domain. A section enable circuit generates a multi-word line driver signal in the first voltage domain based on the level of the first and second section enable signals.
In the first voltage domain, a logical high is represented by a first voltage, while in the second voltage domain, a logical high is represented by a second voltage different from the first voltage. The pre-section enable signal is in a third voltage domain, and the second voltage domain is intermediate to the first and third voltage domains.
The section enable circuit includes a first transistor that couples a node to a voltage representing a logical high in the first voltage domain when the first section enable signal is inactive. It also includes a second transistor that couples a ground voltage representing a logical low in the first voltage domain to the node when the second section enable signal is active. The level of the multi-word line driver signal is determined by the voltage of the node.
The section enable signal driver consists of a first transistor that couples a node to a voltage representing a logical high in the second voltage domain when the pre-section enable signal is active. An inverter provides an inverted pre-section enable signal, and a second transistor couples the node to a ground voltage representing a logical low in the second voltage domain when the inverted pre-section enable signal is active.
The patent also describes a row decoder that generates a word line driver signal based on the voltage of a node. The row decoder includes a first transistor and a second transistor that couple the first voltage and ground voltage, respectively, to the node based on the states of first and second signals. A third transistor couples the node of the second transistor to the ground voltage based on the state of a third signal.
The method described in the patent involves decoding a row address into a section pre-enable signal and generating first and second section enable signals in different voltage domains based on the section pre-enable signal. A multi-word line driver signal is then provided based on the first and second section enable signals. The method also includes activating word lines of a memory array based on the multi-word line driver signal.
Overall, this patent presents an apparatus and method for generating multi-word line driver signals in different voltage domains, allowing for efficient and reliable operation of memory arrays.
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