United Microelectronics has been granted a patent for a method of fabricating a semiconductor device. The method involves forming magnetic tunneling junctions (MTJs) on a substrate, applying a passivation layer using atomic layer deposition (ALD), removing the passivation layer adjacent to the MTJs through etching, and then applying an ultra low-k (ULK) dielectric layer. The passivation layer is designed to have a curve concave downward directly on top of the first MTJ. GlobalData’s report on United Microelectronics gives a 360-degree view of the company including its patenting strategy. Buy the report here.

According to GlobalData’s company profile on United Microelectronics, quantum dot devices was a key innovation area identified from patents. United Microelectronics's grant share as of September 2023 was 81%. Grant share is based on the ratio of number of grants to total number of patents.

Method for fabricating semiconductor device with passivation layer

Source: United States Patent and Trademark Office (USPTO). Credit: United Microelectronics Corp

A recently granted patent (Publication Number: US11778922B2) describes a method for fabricating a semiconductor device. The method involves several steps to form a magnetic tunneling junction (MTJ) and a passivation layer on a substrate.

In the first claim, the method begins with the formation of a first MTJ on the substrate. An atomic layer deposition (ALD) process is then performed to create a passivation layer on top of the first MTJ. Next, an etching process is used to remove the passivation layer adjacent to the first MTJ. Finally, an ultra low-k (ULK) dielectric layer is formed on the passivation layer, with the passivation layer having a curve concave downward directly on top of the first MTJ.

The second claim expands on the first claim by adding the formation of a second MTJ on the substrate. The passivation layer is formed on both the first and second MTJs, with an opening created between them. The etching process can be performed to expand the opening. The passivation layer can have a curve concave upward between the first and second MTJs or a curve concave downward directly on top of the second MTJ.

The seventh claim introduces a different method for fabricating a semiconductor device. The substrate includes a MTJ region and a logic region. The first MTJ is formed on the MTJ region, and a high-density plasma (HDP) process is used to create a passivation layer on top of it. An ultra low-k (ULK) dielectric layer is then formed on the passivation layer, with the bottom surface of the ULK dielectric layer on the MTJ region being lower than the top surface of the first MTJ.

Similar to the second claim, the eighth claim includes the formation of a second MTJ and the creation of an opening between them. The passivation layer is formed on both MTJs, and an etching process is performed to remove the passivation layer adjacent to the first and second MTJs. The passivation layer can have a curve concave upward between the first and second MTJs or a curve concave downward directly on top of either MTJ.

Overall, this patent describes methods for fabricating semiconductor devices with specific arrangements of MTJs and passivation layers. These methods aim to improve the performance and functionality of the devices by utilizing ALD and HDP processes, as well as specific materials for the passivation layer.

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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.