Soitec has filed a patent for a carrier substrate made of monocrystalline silicon. The substrate has a front face and a back face, and consists of three regions: a surface region with less than 10 crystal-originated particles (COPs), an upper region with low interstitial oxygen content and high resistivity, and a lower region with a high concentration of micro-defects. The patent also includes a method for manufacturing such a substrate. GlobalData’s report on Soitec gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Soitec, 3D memory devices was a key innovation area identified from patents. Soitec's grant share as of September 2023 was 46%. Grant share is based on the ratio of number of grants to total number of patents.
Carrier substrate with low particle and defect concentrations
A recently filed patent (Publication Number: US20230317496A1) describes a carrier substrate made of monocrystalline silicon with specific characteristics. The substrate has a front face and a back face, and it consists of three regions.
The first region is a surface region that extends from the front face to a depth of between 800 nm and 2 microns. This surface region has fewer than ten crystal-originated particles (COPs), which are undesirable defects.
The second region is an upper region that extends from the front face to a depth of between a few microns and 40 microns. This upper region has an interstitial oxygen content lower than or equal to 7.5E17 Oi/cm3 and a resistivity higher than 500 ohm·cm. In some embodiments, the resistivity of the upper region is higher than or equal to 750 ohm·cm.
The third region is a lower region that extends between the upper region and the back face. This lower region has a micro-defect concentration higher than or equal to 1E8/cm3. In some embodiments, the micro-defect concentration in the lower region is between 1E8/cm3 and 3E10/cm3.
The patent also describes a silicon-on-insulator (SOI) structure that includes the carrier substrate. The SOI structure consists of a working layer, a dielectric layer, and the carrier substrate. The working layer is disposed on the dielectric layer, which is in turn disposed on the carrier substrate. The carrier substrate has the same characteristics as described above. In addition, the working layer has a thickness of less than 50 nm, and the dielectric layer has a thickness of between 10 nm and 150 nm.
Furthermore, the patent discusses an electronic component for radiofrequency or low-power logic application that includes the SOI structure described above. The electronic component also includes at least one transistor disposed on and/or in the working layer of the SOI structure.
The patent further provides a method for manufacturing the carrier substrate. The method involves providing a substrate made of monocrystalline silicon with specific interstitial oxygen content and resistivity. The substrate undergoes a first heat treatment to form the surface region and the upper region. Then, a second heat treatment is applied to form the lower region. The second heat treatment involves a sequence of annealing at specific temperatures.
In summary, the patent describes a carrier substrate made of monocrystalline silicon with specific characteristics, a silicon-on-insulator structure incorporating the carrier substrate, an electronic component utilizing the SOI structure, and a method for manufacturing the carrier substrate. These innovations aim to improve the performance and reliability of electronic devices.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
